1. Technical Field of the Invention
The present invention relates to the field of digital data transfer, and more particularly, to a digital phase-locked loop that recovers clock information from a stream of encoded data.
2. Description of Related Art
Data encoding allows the transmission of clock and data information over the same medium. It saves the need to transmit the clock and data signals over separate mediums as would normally be required for synchronous data. Some well-known encoding schemes are NRZ (non-return to zero); NRZI (non-return to zero inverted), Manchester (biphase level) and FM encoding. A digital phase-locked loop (DPLL) is used to recover clock information from a data stream that has been encoded in one of these formats. Depending on the type of encoding, the DPLL is driven by a clock at different rates, for example, at 32 (NRZI) or 16 (FM) times the data rate. A DPLL will use this clock, along with the input data stream, to generate a receive clock for the data. The input data stream will then be sampled according to this receive clock.
It is ideal to perform the sampling of the input data stream in the middle of the bit times of the individual bits in the input data stream. This ideal sampling will occur when a counter in the DPLL, used to count the clock pulses driving the DPLL, is properly synchronized to the rising and falling edges of the input data stream. In the past, DPLL's have used up/down counters to perform a count of the clock pulses. The DPLL would then Generate a transition in the receive clock according to the value in this counter, the transition in the receive clock triggering the sampling of the data.
It is possible for the counter in a DPLL to become improperly synchronized to the rising and falling edges of the bit boundaries in the data stream, thereby causing the sampling to not occur in the middle of each bit time. Various schemes have been utilized in the prior art to re-synchronize the counter. For example, a DPLL manufactured by Zilog operates by shifting (when there is improper synchronization) the count laterally (plus or minus) by one bit at a time until proper synchronization is achieved. This lateral shifting by a single bit at a time causes the re-synchronization to occur relatively slowly.
In another DPLL, described in U.S. Pat. No. 5,131,015 and commonly assigned to Cirrus Logic, Inc. of California, different values of an adjustment are applied to a count register. This adjusts the count and thereby the phase in order to center data transitions so that these transitions will be detected when the value in the count register is equal to zero. This condition indicates that the DPLL is perfectly synchronized to the received data stream. Like the Zilog DPLL, the DPLL described in U.S. Pat. No. 5,131,015 uses an up/down counter and provides a relatively complicated scheme for re-synchronizing the counter and thereby the recovered clock signal.